Hy-Ad001 User Manual
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1
2153C–BDC–04/04
Features
•
Dual ADC with 8-bit Resolution
•
1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode
•
Single or 1:2 Demultiplexed Output
•
LVDS Output Format (100
Ω)
•
500 mVpp Analog Input (Differential Only)
•
Differential or Single-ended 50
Ω PECL/LVDS Compatible Clock Inputs
•
Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)
•
LQFP144 Package
•
Temperature Range:
– 0°C < TA < 70°C (Commercial Grade)
– -40°C < TA < 85°C (Industrial Grade)
•
3-wire Serial Interface
– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– Interlacing Functions:
Offset and Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel
– Internal Static or Dynamic Built-In Test (BIT)
Performance
•
Low Power Consumption: 0.7W Per Channel
•
Power Consumption in Standby Mode: 120 mW
•
1.5 GHz Full Power Input Bandwidth (-3 dB)
•
SNR = 42 dB Typ (6.8 ENOB), THD = -51 dBc, SFDR = -54 dBc at Fs = 1 Gsps
Fin = 500 MHz
•
2-tone IMD3: -54 dBc (499 MHz, 501 MHz) at 1 Gsps
•
DNL = 0.25 LSB, INL = 0.5 LSB
•
Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)
•
Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)
•
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Low Bit Error Rate (10
-13
) at 1 Gsps
Application
•
Instrumentation
•
Satellite Receivers
•
Direct RF Down Conversion
•
WLAN
Dual 8-bit
1 Gsps ADC
AT84AD001B
Smart ADC
Instruction Manual
™
Powerflex 525 User Manual
Table of contentsUser Manual
- Electrical Operating Characteristics
- Typical Characterization Results
- Test and Control Features
- 3-wire Serial Interface Control Setting
- Using the AT84AD001B Dual 8-bit 1 Gsps ADC
- Thermal Characteristics
- Simplified Thermal Model for LQFP 144 20 x 20 x 1.4 mm